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It is observed that organization enhancements to the CPU can improve performance. We have already seen that use
of multiple registers rather than a single a accumulator, and use of cache memory improves the performance
considerably. Another organizational approach, which is quite common, is instruction pipelining.
Pipelining is a particularly effective way of organizing parallel activity in a computer system. The basic idea is very
simple. It is frequently encountered in manufacturing plants, where pipelining is commonly known as an assembly
line operation.
By laying the production process out in an assembly line, product at various stages can be worked on
simultaneously. This process is also referred to as pipelining, because, as in a pipeline, new inputs are accepted at
one end before previously accepted inputs appear as outputs at the other end.
To apply the concept of instruction execution in pipeline, it is required to break the instruction in different task. Each
task will be executed in different processing elements of the CPU.
As we know that there are two distinct phases of instruction execution: one is instruction fetch and the other one is
instruction execution. Therefore, the processor executes a program by fetching and executing instructions, one after
another.
Let and refer to the fetch and execute steps for instruction . Execution of a program consists of a sequence
of fetch and execute steps is shown in the figure on the next slide.
Now consider a CPU that has two separate hardware units, one for fetching instructions and another for executing them. The instruction fetch by the fetch unit is stored in an intermediate storage buffer . The results of execution are stored in the destination location specified by the instruction. For simplicity it is assumed that fetch and execute steps of any instruction can be completed in one clock cycle. The operation of the computer proceeds as follows:
● In the first clock cycle, the fetch unit fetches an instruction (instruction , step ) and stored it in buffer at the end of the clock cycle.
● In the second clock cycle, the instruction fetch unit proceeds with the fetch operation for instruction (step ).
● Meanwhile, the execution unit performs the operation specified by instruction which is already fetched and available in the buffer (step ).
● By the end of the second clock cycle, the execution of the instruction is completed and instruction is available.
● Instruction is stored in buffer replacing , which is no longer needed.
● Step is performed by the execution unit during the third clock cycle, while instruction is being fetched by the fetch unit.
● Both the fetch and execute units are kept busy all the time and one instruction is completed after each clock cycle except the first clock cycle.
● If a long sequence of instructions is executed, the completion rate of instruction execution will be twice that achievable by the sequential operation with only one unit that performs both fetch and execute. Basic idea of instruction pipelining with hardware organization is shown in the figure on the next slide
Now consider a CPU that has two separate hardware units, one for fetching instructions and another for executing them. The instruction fetch by the fetch unit is stored in an intermediate storage buffer . The results of execution are stored in the destination location specified by the instruction. For simplicity it is assumed that fetch and execute steps of any instruction can be completed in one clock cycle. The operation of the computer proceeds as follows:
● In the first clock cycle, the fetch unit fetches an instruction (instruction , step ) and stored it in buffer at the end of the clock cycle.
● In the second clock cycle, the instruction fetch unit proceeds with the fetch operation for instruction (step ).
● Meanwhile, the execution unit performs the operation specified by instruction which is already fetched and available in the buffer (step ).
● By the end of the second clock cycle, the execution of the instruction is completed and instruction is available.
● Instruction is stored in buffer replacing , which is no longer needed.
● Step is performed by the execution unit during the third clock cycle, while instruction is being fetched by the fetch unit.
● Both the fetch and execute units are kept busy all the time and one instruction is completed after each clock cycle except the first clock cycle.
● If a long sequence of instructions is executed, the completion rate of instruction execution will be twice that achievable by the sequential operation with only one unit that performs both fetch and execute. Basic idea of instruction pipelining with hardware organization is shown in the figure on the next slide
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