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Cache Memory
Analysis of large number of programs has shown that a number of instructions are executed repeatedly. This may be
in the form of a simple loops, nested loops, or a few procedures that repeatedly call each other. It is observed that
many instructions in each of a few localized areas of the program are repeatedly executed, while the remainder of the
program is accessed relatively less. This phenomenon is referred to as locality of reference.
Analysis of large number of programs has shown that a number of instructions are executed repeatedly. This may be
in the form of a simple loops, nested loops, or a few procedures that repeatedly call each other. It is observed that
many instructions in each of a few localized areas of the program are repeatedly executed, while the remainder of the
program is accessed relatively less. This phenomenon is referred to as locality of reference.
Now, if it can be arranged to have the active segments of a program in a fast memory, then the tolal execution time
can be significantly reduced. It is the fact that CPU is a faster device and memory is a relatively slower device.
Memory access is the main bottleneck for the performance efficiency. If a faster memory device can be inserted
between main memory and CPU, the efficiency can be increased. The faster memory that is inserted between CPU
and Main Memory is termed as Cache memory. To make this arrangement effective, the cache must be considerably
faster than the main memory, and typically it is 5 to 10 time faster than the main memory. This approach is more
economical than the use of fast memory device to implement the entire main memory. This is also a feasible due to
the locality of reference that is present in most of the program, which reduces the frequent data transfer between
main memory and cache memory.
Operation of Cache Memory
The memory control circuitry is designed to take advantage of the property of locality of reference. Some
assumptions are made while designing the memory control circuitry:
1. The CPU does not need to know explicitly about the existence of the cache.
2. The CPU simply makes Read and Write request. The nature of these two operations are same whether cache is present or not.
3. The address generated by the CPU always refer to location of main memory.
4. The memory access control circuitry determines whether or not the requested word currently exists in the cache.
When a Read request is received from the CPU, the contents of a block of memory words containing the location
specified are transferred into the cache. When any of the locations in this block is referenced by the program, its
contents are read directly from the cache.
The cache memory can store a number of such blocks at any given time.
The correspondence between the Main Memory Blocks and those in the cache is specified by means of a mapping
function.
When the cache is full and a memory word is referenced that is not in the cache, a decision must be made as to
which block should be removed from the cache to create space to bring the new block to the cache that contains the
referenced word. Replacement algorithms are used to make the proper selection of block that must be replaced by the
new one.
When a write request is received from the CPU, there are two ways that the system can proceed. In the first case,
the cache location and the main memory location are updated simultaneously. This is called the store through method
or write through method.
The alternative is to update the cache location only. During replacement time, the cache block will be written back to
the main memory. If there is no new write operation in the cache block, it is not required to write back the cache block
in the main memory. This information can be kept with the help of an associated bit. This bit it set while there is a
write operation in the cache block. During replacement, it checks this bit, if it is set, then write back the cache block in
main memory otherwise not. This bit is known as dirty bit. If the bit gets dirty (set to one), writting to main memory is
required.
This write through method is simpler, but it results in unnecessary write operations in the main memory when a given
cache word is updated a number of times during its cache residency period.
Consider the case where the addressed word is not in the cache and the operation is a read. First the block of the
words is brought to the cache and then the requested word is forwarded to the CPU. But it can be forwarded to the
CPU as soon as it is available to the cache, instead of whole block to be loaded into the cache. This is called load
through, and there is some scope to save time while using load through policy
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